MOSA
16-Bits Stereo Audio DAC
Low Power Consumption
Low Voltage, Excellent PSRR
FEATURES
‧Operation
range: 2.7V~5.5V
‧Excellent
Power Supply Rejection Ratio(PSRR)
‧Low
operating current
‧Low
power consumption
8mW at V
DD
=3.3V (Full scale output )
‧Low
distortion
‧No
zero crossing distortion
‧Wide
dynamic range(16-bit resolution)
‧Voltage
Output
MS6323
16-Bits Stereo Audio DAC
‧Fast
setting time permits 2*, 4*, and 8* oversampling
(serial input) or double speed operation at 4*
oversampling
‧Compatible
with most of the Japanese input formats;
time multiplexed, two's complement, CMOS and TTL
input level, MS6323AS for CMOS level, MS6323T for
TTL level
‧Output
voltage swing is proportional to supply voltage
(V
OPP
=V
DD
/2)
‧
Cost efficient
‧
Space saving package SOP8, MSOP8
APPLICATIONS
‧Multimedia
system
‧MP3,
PDA, Portable Digital Audio.
DESCRIPTION
The MS6323 is a 16-bit voltage-output Digital-to-Analog Converter(DAC). It gives the excellent Power Supply
Rejection Ratio(PSRR). It features extremely low power dissipation, small package size and easy application. The
accuracy of the weight current sources, combined with the unique symmetrical decoding method, preclude zero-
crossing distortion and ensures high quality audio reproduction. These unique features, combined with its exceptional
performance, make the MS6323 ideally suited for use in portable audio equipment. MS6323 is pin and function
compatible with MS6313.
PIN CONFIGURATION
Symbol
BCK
WS
DATA
GND
V
DD
V
OL
Cap
1
2
3
4
5
6
7
Pin
Description
Bit clock input
Word select input
Data input
Ground
Positive supply voltage
Left channel output
Cap
DATA
3
GND
4
BCK
1
WS
2
8
V
OR
7
Cap
MS6323
6
V
OL
5
V
DD
V
OR
8
Right channel output
Pin 7 : Capacitor = 1
μ
F (ripple rejection)
REV1.1
1
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MOSA
BLOCK DIAGRAM
I
BL
MS6323
16-Bits Stereo Audio DAC
R
F
6
V
OUT
LEFT
LEFT OUTPUT LATCH
RIGHT OUTPUT LATCH
I
BR
OP1
V
REF
R
F
8
OP2
V
REF
LEFT BIT SWITCHS
RIGHT BIT SWITCHS
V
OUT
RIGHT
16-BIT WEIGHT
CURRENT DIVIDER
I
REF
REFERENCE
CURRENT
SOURCE
16-BIT WEIGHT
CURRENT DIVIDER
I
REF
REFERENCE
CURRENT
SOURCE
I
BL
I
BR
7
CAP
LEFT INPUT LATCH
BCK
1
REFERENCE
SOURCE
1uF
V
REF
4
GND
WS
2
CONTROL
&
TIMING
RIGHT INPUT LATCH
10uF
0.1uF
DATA
3
5
V
DD
Fig.1
Block diagram.
ORDERING INFORMATION
CMOS input level
Package
8-Pin SOP
8-Pin SOP
8-Pin SOP (lead free)
8-Pin SOP (lead free)
8-Pin MSOP
8-Pin MSOP
8-Pin MSOP (lead free)
8-Pin MSOP (lead free)
TTL input level
Package
8-Pin SOP (lead free)
8-Pin SOP (lead free)
8-Pin MSOP (lead free)
8-Pin MSOP (lead free)
REV1.1
Part number
MS6323ASTR
MS6323ASU
MS6323ASGTR
MS6323ASGU
MS6323ASMTR
MS6323ASMU
MS6323ASMGTR
MS6323ASMGU
Packaging Marking
MS6323AS
MS6323AS
MS6323ASG
MS6323ASG
6323
6323
6323G
6323G
Transport Media
2.5k Units Tape and Reel
100 Units Tube
2.5k Units Tape and Reel
100 Units Tube
3.5k Units Tape and Reel
80 Units Tube
3.5k Units Tape and Reel
80 Units Tube
Part number
MS6323TGTR
MS6323TGU
MS6323TMGTR
MS6323TMGU
Packaging Marking
MS6323TG
MS6323TG
6323TG
6323TG
2
Transport Media
2.5k Units Tape and Reel
100 Units Tube
3.5k Units Tape and Reel
80 Units Tube
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MOSA
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
ESD
T
STG
T
A
T
J
T
S
R
THJA
Positive Supply Voltage
Electrostatic Handling
Storage Temperature Range
Operating Ambient Temperature Range
Maximum Junction Temperature
Soldering Temperature, 10 seconds
Thermal Resistance from Junction to Ambient in Free Air
SOP8
MSOP8
Parameter
MS6323
16-Bits Stereo Audio DAC
Rating
6
-2000 to 2000
-65 to 150
-40 to 85
150
260
210
235
Unit
V
V
℃
℃
℃
℃
℃/W
OPERATING RATINGS
Symbol
V
DD
Supply Voltage
Parameter
Min
2.7
Typ
-
Max
5.5
Unit
V
3.3V ELECTRICAL CHARACTERISTICS
(Ta=25℃, V
DD
=3.3V, V
SS
=0V, f=1kHz, Cap=1uF; unless otherwise specified)
Symbol
DC Characteristics
V
CAP
V
DC
V
FS
I
Q
PSRR
CS
Res
THD+N
S/N
Voltage at CAP
Output DC level
Full scale output voltage
Quiescent current
Power supply rejection ratio
Channel separation
Resolution
Total harmonic distortion plus
noise
Signal-to-noise ratio
V
FS
=0.5V
DD
At code 0000H
CAP=1uF, f=100Hz
CAP=10uF, f=100Hz
1.60
1.60
1.5
-
45
63
78
-
-
-
86
1.65
1.65
1.65
2.0
50
68
84
-
-66
0.05
92
1.70
1.70
1.8
2.3
-
-
-
16
-62
0.08
-
V
V
Vpp
mA
dB
dB
dB
bits
dB
Parameter
Conditions
Min
Typ
Max
Unit
AC Characteristics
%
dB
REV1.1
3
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MOSA
2.7V ELECTRICAL CHARACTERISTICS
(Ta=25℃, V
DD
=2.7V, V
SS
=0V, f=1kHz, Cap=1uF; unless otherwise specified)
Symbol
DC Characteristics
V
CAP
V
DC
V
FS
I
Q
PSRR
CS
Res
THD+N
S/N
Voltage at CAP
Output DC level
Full scale output voltage
Quiescent current
Power supply rejection ratio
Channel separation
Resolution
Total harmonic distortion plus
noise
Signal-to-noise ratio
At code 0000H
CAP=1uF, f=100Hz
CAP=10uF, f=100Hz
V
FS
=0.5V
DD
1.30
1.30
1.2
-
45
63
77
-
-
-
84
Parameter
Conditions
Min
MS6323
16-Bits Stereo Audio DAC
Typ
1.35
1.35
1.35
1.9
49
68
83
-
-66
0.05
90
Max
1.40
1.40
1.5
2.2
-
-
-
16
-62
0.08
-
Unit
V
V
Vpp
mA
dB
dB
dB
bits
dB
AC Characteristics
%
dB
TYPICAL PERFORMANCE CHARACTERISTICS
(Ta=25℃, f=1kHz, Cap=1uF, sampling rate=4fs; unless otherwise specified, )
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
CHANNEL SEPARATION (dB)
QUIESCENT CURRENT (mA)
THD+N (%)
FREQUENCY (Hz)
Quiescent current vs. supply voltage e
THD+N vs. supply voltage
Channel separation vs. frequency
CAP=22uF
CAP=10uF
CAP=22uF
CAP=10uF
CAP=1uF
CAP=1uF
THD+N (%)
V
DD
=2.7V
PSRR (dB)
PSRR (dB)
V
DD
=3.3V
V
DD
=3.3V
V
RR
=-20dBV
V
DD
=2.7V
V
RR
=-20dBV
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
PSRR vs. frequency
REV1.1
PSRR vs. frequency
THD+N vs. frequency
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4
MOSA
TIMING AND DATA FORMAT
MS6323
16-Bits Stereo Audio DAC
The MS6323 accepts input serial data formats of 16-bit word length. Left and right data words are time
multiplexed. The MSB must always be first. The format of data input is shown in Figs. 2 and 3. With a HIGH level on
the word select input (WS), data is placed in the left input register and with LOW level on the WS input, data is placed
in the right register (Fig. 1). The data in the input registers are simultaneously latched in the output registers which
control the bit switches. Internal bias currents I
BL
and I
BR
are each added to the full scale output current I
FS
in order to
achieve the maximum dynamic range at the outputs of OP1 and OP2(Fig. 1). In this way the maximum dynamic range
is achieved over the entire power supply range.
WS
t
r
t
HB
t
f
LEFT
RIGHT
t
LB
t
HW
t
SW
BCK
t
cr
LSB
MSB
t
SD
t
HD
DATA
Fig.2
Timing and input signals.
WS
LEFT
RIGHT
BCK
DATA
2
1
0
15
MSB
14
13
2
1
0
LSB
15
MSB
14
13
2
1
0
LSB
Fig.3
Format of input signals.
REV1.1
5
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